Scientific interface for the Amstrad PCW

An important requirement was that the interface be kept modular so that sections could be easily omitted or added later. Figures 5 to 9 show optional circuitry that may be included as required. In addition, extra address decoding has been provided to reserve a total of eight 8-bit port addresses, allowing four for the present circuitry and another four for adding later a serial interface and eprom programmer.

Address lines from the expansion connector are taken to decoders IC201 and IC202 (Fig.2, April issue, page 455) which provide a separate read and write select line for each of the four ports on the card. Port addresses and their hardware assignments (Fig.4) have been chosen in consultation with Amstrad to ensure future upgrade capability.

Any address access to the card triggers IC203, a monostable which drives an 'access' led. This has proved useful during the construction of both hardware. Data bus transceiver IC207 is enabled by any card access and provides additional protection and fanout.

Figure 5 shows the eight-bit digital output. A single octal latch IC401 latches data written to port address A1. The data output is displayed on leds but no attempt has been made to add extra output buffering. This is the only external connection to the interface where protection is not available since it adds significant complexity if speed or other compromises are to be avoided. Data written to this address remains latched until changed.

Figure 6 shows the eight-way input circuitry. Input signals are pulled down by R501 and the Schmitt triggers are fed via R502. This arrangement is highly recommended since it provides very low loading and can be connected directly to 15V c-mos or arbitrary logic levels, so long as the threshold of around 2V is accommodated.

The level of protection is very high: and although it is to be discouraged, an input can be connected to the mains without damage other than increased heating of the input resistors. A speed degradation of 1μs or so is due to R502, but this is small compared with the obtainable processor i/o rate of around 20μs.

The digital to analogue converter circuit (Fig.7) can be added to the address decoding of Fig.2 to form a powerful waveform synthesizer.

The eight-bit converter is a bus-orientated device that latches data written to port address A2 and provides an output voltage controlled from zero to its 2.55V internal reference. This is fed to the optional circuitry of Fig.10 which provides scale and offset adjustment as well as i/o protection.

Figure 8 shows the high-speed eight-bit successive approximation a-to-d converter IC701 with its sample and hold buffer amplifier. A minimum system would comprise the address decoding (Fig.2), the d.a.c. (Fig.7), a simple inverter to derive a negative supply and this circuit to provide almost all of the waveform recording, replay and plotting facilities.

This circuit will digitize an input waveform via software at up to 25kHz, although the a-to-d conversion time is set by the clock generator IC702 to around 10μs (100k samples per second). During conversion the Busy output is used to force a Hold condition on IC703 to ensure no input change. This allows the fastest sampling of dynamic waveforms without external filtering.

Conversion is started by a write to port address A0. Internal circuitry then performs the conversion and data is available for reading at port A2. The fixed, short conversion time eliminates the need to take the Busy signal to the processor.

For more precise but slower measurements, a dual-slope a-to-d converter is available (Fig.9). This is an auto-zeroing, b.c.d. output device which accepts an input voltage of either polarity in the range +2.000V to -2,000V and provides four 4-bit b.c.d. words at Q0-Q3 together with strobe signals DS0-DS3 which identify their significance.

The device is ratiometric and requires an external 2V reference. The d-to-a converter reference is slightly higher at a nominal 2.55V and for accurate reading of the applied voltage this reference may be adjusted to 2.000 volts by VR801. The adjustment is only needed if the analogue signal conditioning is omitted, since a variable gain factor is inherent in that section. In this case VR801 can be replaced by a link, and 100kΩ fitted instead of the 82kΩ shown.

The processor reads each b.c.d. digit and its strobe via IC802 (timing diagram Fig. 10).

A read cycle begins with the end-of-conversion signal EOC which is stretched by IC804 to ensure its visibility to the processor read loop. The processor then loops waiting for the first strobe (DS0) to read the most significant b.c.d. digit, followed by strobes for the other three digits. Strobes DS1 and DS3 are combined since there is no timing ambiguity.

Extra information is available coded into the m.s.d. (inset in Fig.10). The accompanying software extracts the half-digit and polarity and stores overrange and underrange in mernory undecoded.

A quad op-amp IC801 (not shown) buffers and conditions the analogue signals both inward and outward. The circuits allow a scale factor to be set from around 0.5 to 5 times gain, together with an offset adjustment to suit either bipolar or unipolar levels.

A switch S101 allows a.c. coupling if required.

Physical layout of the interface is important since it must mate wih the connector at the rear of the Amstrad PCW enclosure. This connector (Fig.3) carries all the bus signals and will not, in general, permit the use of ribbon cable out to a remote unit.

The prototype unit was therefore constructed in two sections: a logic section with the converters on the rear of the computer, and the i/o section remote on ribbon cable. But it would be better to construct the unit in one piece to mount directly on the computer.

It may be difficult to find a connector designed to fit the rear expansion port. Unless the connector supplied in the kit is to be used, an ordinary 0.1 inch pitch edge-connector can be adapted to fit.

If you adapt an ordinary connector, use of the Amstrad polarizing slot is not recommended since it is placed between the 0.1 inch pitches and so cannot be used with the usual 'pin substitute' type polarized connectors. The best alternative is to rernove the outer unwanted pins from a longer connector and to fabricate end-cheeks which will locate the connector snugly on the outer end of the exposed Amstrad p.c.b. without the need to insert anything in the slot between the pins. The end-cheeks can be made using pieces or p.c.b. or other material dropped into the connector and fixed with epoxy before being pushed on to the Amstrad for location as the expoxy cures. Be careful not to be too generous with the epoxy, or the connector may become a permanent feature of the computer! Wiping the Amstrad connector with a silicone-based preparation such as WD-40 will prevent stray expoxy from adhering.

Begin testing with the address decoding circuit of Fig.2. Having checked it, fit it to the computer and run the program PORT. This asks for the selection of a read-data or write-data fast software loop, allowing an ordinary oscilloscope to be triggered from TP201 (the card enable line) and so probe any address or data line.

If there has been an error in construction, it may be that no trigger pulse appears at TP201. In this case, trigger the 'scope from IOREQ (i/o request) using the PORT program and examine the inputs and outputs of the address decoders to establish why the required port address is not being correctly decoded. On the prototype the +5V rail takes around 200mA and the +12V a few mA.

After one or more of the interface functions has been added it can be tested fully using another supplied test program SIN.