PAL18L4 PAL DESIGN SPECIFICATION P7083 VINCENT COLI 04/19/82 MEMORY MAPPED I/O MMI SUNNYVALE, CALIFORNIA A0 A1 A2 A3 A4 A5 A6 A7 A8 /RD /WR GND A9 A10 A11 A12 /READ /WRITE /AUX2 /AUX1 A13 A14 A15 VCC READ = /A15*/A14*/A13* A12* A11* A10* A9* A8 ;SELECT PORT1 * /A7 * A6 * A5 * A4 */A3 * A2 * A1*/A0 ; (1F76) * RD ;READ STROBE WRITE = /A15*/A14*/A13* A12* A11* A10* A9* A8 ;SELECT PORT1 * /A7 * A6 * A5 * A4 */A3 * A2 * A1* A0 ; (1F77) * WR ;WRITE STROBE AUX1 = /A15*/A14*/A13* A12* A11* A10* A9* A8 ;SELECT PORT0 * /A7 * A6 * A5 * A4 * A3 */A2 */A1*/A0 ; (1F78) AUX2 = /A15*/A14*/A13* A12* A11* A10* A9* A8 ;SELECT PORT1 * /A7 * A6 * A5 * A4 * A3 */A2 */A1* A0 ; (1F79) FUNCTION TABLE A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /RD /WR /READ /WRITE /AUX1 /AUX2 ;-ADDRESS INPUTS- ;111111 STROBES --PORT ENABLE OUTPUTS--- ;5432109876543210 /RD /WR /READ /WRITE /AUX1 /AUX2 COMMENTS ------------------------------------------------------------------------------- LLLLHHHHLHHHHLLL L L H H H H TEST 0F78 LLLHHHHLLHHHHLLL L L H H H H TEST 1E78 LLLHHHHHHHHHHLLL L L H H H H TEST 1FF8 LLLHHHHHLHHHLLLL L L H H H H TEST 1F70 LLLHHHHHLHHHLHHL H L H H H H TEST 1F76 (NO RD STROBE) LLLHHHHHLHHHLHHL L L L H H H TEST 1F76 (READ ENABLE) LLLHHHHHLHHHLHHH L H H H H H TEST 1F77 (NO WR STROBE) LLLHHHHHLHHHLHHH L L H L H H TEST 1F77 (WRITE ENABLE) LLLHHHHHLHHHHLLL L L H H L H TEST 1F78 (AUX1 ENABLE) LLLHHHHHLHHHHLLH L L H H H L TEST 1F79 (AUX2 ENABLE) LLLHHHHHLHHHHLHL L L H H H H TEST 1F7A LLLHHHHHHHHHHLLH L L H H H H TEST 1FF9 LLLHHHHLLHHHHLLH L L H H H H TEST 1E79 LLHHHHHHLHHHHLLH L L H H H H TEST 3F79 LLLLLLLLLLLLLLLL L L H H H H TEST ALL L'S HHHHHHHHHHHHHHHH L L H H H H TEST ALL H'S LHLHLHLHLHLHLHLH L L H H H H TEST ODD CHECKERBOARD HLHLHLHLHLHLHLHL L L H H H H TEST EVEN CHECKERBOARD ------------------------------------------------------------------------------- DESCRIPTION THIS PAL PROVIDES A SINGLE CHIP DECODER FOR USE IN MEMORY MAPPED I/O OPERATIONS REQUIRING FOUR ACTIVE LOW PORT ENABLES AND FULL 16-BIT DECODE WITH TWO TWO STROBE LINES (/RD AND /WR). EQUATION TERMS CAN BE CHANGED TO ACCOMMODATE ANY 16-BIT ADDRESS. THE PAL WILL MONITOR THE SYSTEM MEMORY ADDRESS BUS (A15-A0) AND DECODE THE SPECIFIED MEMORY ADDRESS WORD (1F76,1F77,1F78,1F79) TO PRODUCE A PORT ENABLE FOR READ, WRITE, AUXILARY UNIT 1 (AUX1), AUXILARY UNIT 2 (AUX2) AS SHOWN IN THE FOLLOWING TABLE: ------------------------------ ! ADDRESS ! STROBES ! PORT ! ! INPUTS ! /RD /WR ! ENABLE ! !---------!---------!--------! ! 1F76 ! L X ! READ ! ! 1F77 ! X L ! WRITE ! ! 1F78 ! X X ! AUX1 ! ! 1F79 ! X X ! AUX2 ! ------------------------------