PAL16R8 PAL DESIGN SPECIFICATION P7097 WILLY VOLDAN 09/09/82 SHAFT ENCODER No. 2 MMI GMBH MUNICH CLK PHI0 PHI90 X4 NC NC NC NC /SET GND /OC UD NC S4 S3 S2 S1 NC COUNT VCC /S1 := /PHI0 ;CHECK FOR PHI0 + SET ;INITIALIZE S1=L /S3 := /PHI90 ;CHECK FOR PHI90 + SET ;INITIALIZE S3=L /S2 := S1 ;CHECK FOR /S1 + SET ;INITIALIZE S2=L /S4 := S3 ;CHECK FOR /S3 + SET ;INITIALIZE S4=L /COUNT := S1* S2*/S3* S4 ;THIS OUTPUT ALTERNATES + /S1*/S2* S3*/S4 ;BETWEEN HIGH AND LOW WITH + /S1* S2*/S3*/S4* X4 ;HALF OR QUARTER THE + S1*/S2* S3* S4* X4 ;CLK FREQUENCY + S1* S2* S3*/S4 + /S1*/S2*/S3* S4 + /S1* S2* S3* S4* X4 + S1*/S2*/S3*/S4* X4 /UD := /S1* S2*/S3* S4 ;THIS OUTPUT DETERMINES + /S1* S2* S3* S4 ;IF SIGNAL PHI0 LEADS + /S1* S2* S3*/S4 ;OR LAGS SIGNAL PHI90 + S1* S2* S3*/S4 + S1*/S2* S3*/S4 + S1*/S2*/S3*/S4 + S1*/S2*/S3* S4 + /S1*/S2*/S3* S4 FUNCTION TABLE CLK /OC /SET PHI0 PHI90 X4 S1 S2 S3 S4 COUNT UD ;---CONTROLS--- --INPUTS-- X SSSS -OUTPUTS- ;CLK /OC /SET PHI0 PHI90 4 1234 COUNT UD COMMENTS ------------------------------------------------------------------------------- C L L X X X LLLL H H CLEAR REGISTERS C L H L L L LHLH H H COUNT UP X4=L C L H H L L HHLH H L C L H H L L HLLH L H C L H H H L HLHH H L C L H H H L HLHL H H C L H L H L LLHL H L C L H L H L LHHL L H C L H L L L LHLL H L C L H L L L LHLH H H C L H H L L HHLH H L C L H H L L HLLH L H C L H H H L HLHH H L C L H H H L HLHL H H C L H L H L LLHL H L C L H L H L LHHL L H C L H L L H LHLL H L COUNT UP X4=L C L H L L H LHLH L H C L H H L H HHLH H L C L H H L H HLLH L H C L H H H H HLHH H L C L H H H H HLHL L H C L H L H H LLHL H L C L H L H H LHHL L H C L H L L H LHLL H L C L H L L H LHLH L H C L H H L H HHLH H L C L H H L H HLLH L H C L H H H H HLHH H L C L H H H H HLHL L H C L L X X X LLLL H L CLEAR REGISTERS C L H L L L LHLH H H COUNT DOWN X4=L C L H L H L LHHH H L C L H L H L LHHL H L C L H H H L HHHL H L C L H H H L HLHL L L C L H H L L HLLL H L C L H H L L HLLH H L C L H L L L LLLH H L C L H L L L LHLH L L C L H L H L LHHH H L C L H L H L LHHL H L C L H H H L HHHL H L C L H H H L HLHL L L C L H H L L HLLL H L C L H H L L HLLH H L C L H L L H LLLH H L COUNT DOWN X4=H C L H L L H LHLH L L C L H L H H LHHH H L C L H L H H LHHL L L C L H H H H HHHL H L C L H H H H HLHL L L C L H H L H HLLL H L C L H H L H HLLH L L C L H L L H LLLH H L C L H L L H LHLH L L C L H L H H LHHH H L C L H L H H LHHL L L C L H H H H HHHL H L C L H H H H HLHL L L X H X X X X ZZZZ Z Z TEST HI-Z ------------------------------------------------------------------------------- DESCRIPTION THIS PAL16R8 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED CONTROLLERS AND OPTICAL DEVICES. THE "COUNT" OUTPUT OF THE PAL IS NORMALLY HIGH. DURING SHAFT ENCODING THIS OUTPUT ALTERNATES BETWEEN HIGH AND LOW. INPUT "X4" SELECTS BETWEEN HALF (X4=H) OR QUARTER (X4=L) CLK FREQUENCY OF THE "COUNTER" OUTPUT. OUTPUT "UD" DETERMINES WHETHER SIGNAL PHI0 LEADS (UD=H) OR LAGS (UD=L) SIGNAL PHI90. THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN 74S697 TYPE UP/DOWN COUNTER. THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE CHANGED ACCORDING TO THE PC-BOARD LAYOUT.