PAL16R4 PAL DESIGN SPECIFICATION P7096 WILLY VOLDAN 09/09/82 SHAFT ENCODER No. 1 MMI GMBH MUNICH CLK PHI0 PHI90 X4 NC NC NC NC /SET GND /OC DOWN NC S4 S3 S2 S1 NC UP VCC /S1 := /PHI0 ;CHECK FOR PHI0 + SET ;INITIALIZE S1=L /S2 := /S1 ;CHECK FOR S1 + SET ;INITIALIZE S2=L /S3 := /PHI90 ;CHECK FOR PHI90 + SET ;INITIALIZE S3=L /S4 := /S3 ;CHECK FOR S3 + SET ;INITIALIZE S4=L IF (VCC) /DOWN = S1* S2* S3*/S4* PHI0* PHI90 ;PHI0 LEADS PHI90 + /S1*/S2*/S3* S4*/PHI0*/PHI90 ;PHI0 LEADS PHI90 + S1*/S2*/S3*/S4* PHI0*/PHI90 ;PHI0 LEADS PHI90 + /S1* S2* S3* S4*/PHI0* PHI90 ;PHI0 LEADS PHI90 IF (VCC) /UP = /S1*/S2* S3*/S4*/PHI0* PHI90 ;PHI90 LEADS PHI0 + S1* S2*/S3* S4* PHI0*/PHI90 ;PHI90 LEADS PHI0 + S1*/S2* S3* S4* PHI0* PHI90 ;PHI90 LEADS PHI0 + /S1* S2*/S3*/S4*/PHI0*/PHI90 ;PHI90 LEADS PHI0 FUNCTION TABLE CLK /OC /SET PHI0 PHI90 S4 S3 S2 S1 UP DOWN ;---CONTROLS--- --INPUTS-- SSSS OUTPUTS ;CLK /OC /SET PHI0 PHI90 4321 UP DOWN COMMENTS ------------------------------------------------------------------------------- C L L X X LLLL H H CLEAR REGISTERS C L H L L LLLL H H C L H L L LLLL H H C L H L H LHLL L H COUNT UP C L H L H HHLL H H C L H H H HHLH L H COUNT UP C L H H H HHHH H H C L H H L HLHH L H COUNT UP C L H H L LLHH H H C L H L L LLHL L H COUNT UP C L H L L LLLL H H C L H L H LHLL L H COUNT UP C L H L H HHLL H H C L H H H HHLH L H COUNT UP C L H H H HHHH H H C L H H L HLHH L H COUNT UP C L H H L LLHH H H C L H L L LLHL L H COUNT UP C L H L L LLLL H H C L H L H LHLL L H COUNT UP C L H L H HHLL H H C L H H H HHLH L H COUNT UP C L H H H HHHH H H C L H H L HLHH L H COUNT UP C L H H L LLHH H H C L H L L LLHL L H COUNT UP C L H L L LLLL H H C L L X X LLLL H H CLEAR REGISTERS C L H L L LLLL H H C L H L L LLLL H H C L H H L LLLH H L COUNT DOWN C L H H L LLHH H H C L H H H LHHH H L COUNT DOWN C L H H H HHHH H H C L H L H HHHL H L COUNT DOWN C L H L H HHLL H H C L H L L HLLL H L COUNT DOWN C L H L L LLLL H H C L H H L LLLH H L COUNT DOWN C L H H L LLHH H H C L H H H LHHH H L COUNT DOWN C L H H H HHHH H H C L H L H HHHL H L COUNT DOWN C L H L H HHLL H H C L H L L HLLL H L COUNT DOWN C L H L L LLLL H H C L H H L LLLH H L COUNT DOWN C L H H L LLHH H H C L H H H LHHH H L COUNT DOWN C L H H H HHHH H H C L H L H HHHL H L COUNT DOWN C L H L H HHLL H H C L H L L HLLL H L COUNT DOWN C L H L L LLLL H H X H X X X ZZZZ X X TEST HI-Z ------------------------------------------------------------------------------- DESCRIPTION: THIS PAL16R4 IMPLEMENTS A TWO CHANNEL SHAFT ENCODER OF THE TYPE USED IN SPEED CONTROLLERS AND OPTICAL DEVICES. BOTH THE "UP" AND "DOWN" OUTPUTS OF THE PAL ARE NORMALLY HIGH. WHEN THE SIGNAL AT THE "PHI0" INPUT LEADS THE SIGNAL AT THE "PHI90" INPUT, THE "DOWN" OUTPUT ALTERNATES BETWEEN HIGH AND LOW LEVELS AT HALF THE "CLK" FREQUENCY RATE. ALSO, WHEN THE SIGNAL AT THE "PHI0" INPUT LAGS THE SIGNAL AT THE "PHI90" INPUT, THE "UP" OUTPUT ALTERNATES BETWEEN HIGH AND LOW LEVELS AT HALF THE "CLK" FREQUENCY RATE. THE SHAFT ENCODER FEATURES THE CONFIGURATION AND OUTPUT POLARITY TO DRIVE AN 74S193 TYPE UP/DOWN COUNTER. THIS DESIGN WITH GLITCHFREE OUTPUTS WILL BE EXTREMELY USEFUL IN ELECTRICALLY NOISY ENVIRONMENTS. THE PINNING IS GIVEN AS A FIRST PROPOSAL AND CAN BE CHANGED ACCORDING TO THE PC-BOARD LAYOUT.