PAL16R4 PAL DESIGN SPECIFICATION P7093 VINCENT COLI 06/21/82 8 INPUT REGISTERED PRIORITY ENCODER WITH INTERRUPT FLAG MMI SUNNYVALE, CALIFORNIA CLK I0 I1 I2 I3 I4 I5 I6 I7 GND /OC /E4 /E3 Q3 Q2 Q1 Q0 E2 E1 VCC /Q0 := /I0* I1 ;DECODE I0=L AND I1=H + /I0*/I1*/I2* I3 ;DECODE I0-2=L AND I3=H + /I0*/I1*/I2*/I3*/I4* I5 ;DECODE I0-4=L AND I5=H + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7 ;DECODE I0-6=L AND I7=H /Q1 := /I0*/I1* I2 ;DECODE I0-1=L AND I2=H + /I0*/I1*/I2* I3 ;DECODE I0-2=L AND I3=H + /I0*/I1*/I2*/I3*/I4*/I5* I6 ;DECODE I0-5=L AND I6=H + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7 ;DECODE I0-6=L AND I7=H /Q2 := /I0*/I1*/I2*/I3* I4 ;DECODE I0-3=L AND I4=H + /I0*/I1*/I2*/I3*/I4* I5 ;DECODE I0-4=L AND I5=H + /I0*/I1*/I2*/I3*/I4*/I5* I6 ;DECODE I0-5=L AND I6=H + /I0*/I1*/I2*/I3*/I4*/I5*/I6* I7 ;DECODE I0-6=L AND I7=H /Q3 := E1* E2* E3* E4* I0 ;INTERRUPT FLAG (I0) + E1* E2* E3* E4* I1 ;INTERRUPT FLAG (I1) + E1* E2* E3* E4* I2 ;INTERRUPT FLAG (I2) + E1* E2* E3* E4* I3 ;INTERRUPT FLAG (I3) + E1* E2* E3* E4* I4 ;INTERRUPT FLAG (I4) + E1* E2* E3* E4* I5 ;INTERRUPT FLAG (I5) + E1* E2* E3* E4* I6 ;INTERRUPT FLAG (I6) + E1* E2* E3* E4* I7 ;INTERRUPT FLAG (I7) FUNCTION TABLE CLK /OC E1 E2 /E3 /E4 I7 I6 I5 I4 I3 I2 I1 I0 Q3 Q2 Q1 Q0 ; CHIP ----FOUR----- 8 INPUTS OUTPUTS ;CONTROL INPUT ENABLES IIIIIIII Q QQQ ;CLK /OC E1 E2 /E3 /E4 76543210 3 210 COMMENTS ------------------------------------------------------------------------------- C L L H L L XXXXXXXH H HHH I0 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXXXXXXH H HHH I0 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXXXXXXH H HHH I0 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXXXXXXH H HHH I0 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXXXXXXH L HHH I0 INTERRUPT (HIGHEST PRIORITY) C L L H L L XXXXXXHL H HHL I1 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXXXXXHL H HHL I1 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXXXXXHL H HHL I1 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXXXXXHL H HHL I1 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXXXXXHL L HHL I1 INTERRUPT C L L H L L XXXXXHLL H HLH I2 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXXXXHLL H HLH I2 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXXXXHLL H HLH I2 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXXXXHLL H HLH I2 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXXXXHLL L HLH I2 INTERRUPT C L L H L L XXXXHLLL H HLL I3 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXXXHLLL H HLL I3 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXXXHLLL H HLL I3 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXXXHLLL H HLL I3 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXXXHLLL L HLL I3 INTERRUPT C L L H L L XXXHLLLL H LHH I4 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXXHLLLL H LHH I4 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXXHLLLL H LHH I4 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXXHLLLL H LHH I4 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXXHLLLL L LHH I4 INTERRUPT C L L H L L XXHLLLLL H LHL I5 INTERRUPT NOT ENABLED (E1=L) C L H L L L XXHLLLLL H LHL I5 INTERRUPT NOT ENABLED (E2=L) C L H H H L XXHLLLLL H LHL I5 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XXHLLLLL H LHL I5 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XXHLLLLL L LHL I5 INTERRUPT C L L H L L XHLLLLLL H LLH I6 INTERRUPT NOT ENABLED (E1=L) C L H L L L XHLLLLLL H LLH I6 INTERRUPT NOT ENABLED (E2=L) C L H H H L XHLLLLLL H LLH I6 INTERRUPT NOT ENABLED(/E3=H) C L H H L H XHLLLLLL H LLH I6 INTERRUPT NOT ENABLED(/E4=H) C L H H L L XHLLLLLL L LLH I6 INTERRUPT C L L H L L HLLLLLLL H LLL I7 INTERRUPT NOT ENABLED (E1=L) C L H L L L HLLLLLLL H LLL I7 INTERRUPT NOT ENABLED (E2=L) C L H H H L HLLLLLLL H LLL I7 INTERRUPT NOT ENABLED(/E3=H) C L H H L H HLLLLLLL H LLL I7 INTERRUPT NOT ENABLED(/E4=H) C L H H L L HLLLLLLL L LLL I7 INTERRUPT (LOWEST PRIORITY) C L H H L L LLLLLLLL H HHH NO INTERRUPT INPUT (Q3=H) X H X X X X XXXXXXXX Z ZZZ TEST HI-Z ------------------------------------------------------------------------------- DESCRIPTION THE 8 INPUT REGISTERED PRIORITY ENCODER ACCEPTS SIXTEEN ACTIVE-LOW INPUTS (I0-I7) TO LOAD THE BINARY WEIGHTED CODE OF THE PRIORITY ORDER INTO THE OUTPUT REGISTER (Q2-Q0) ON THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE FOUR ENABLE INPUTS ARE TRUE (E1=H,E2=H,/E3=L,/E4=L). A PRIORITY IS ASSIGNED TO EACH INPUT SO THAT WHEN TWO INPUTS ARE SIMULTANEOUSLY ACTIVE, THE INPUT WITH THE HIGHEST PRIORITY IS LOADED INTO THE OUTPUT REGISTER. THEREFORE THE HIGHEST PRIORITY INPUT (I0=H) PRODUCES HHH IN THE OUTPUT REGISTER AND THE LOWEST PRIORITY INPUT (I7=H) PRODUCES LLL IN THE OUTPUT REGISTER. THE PRIORITY INTERRUPT ENCODER REGISTERS (Q3-Q0) ARE UPDATED ON THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE FOUR ENABLE INPUTS ARE TRUE (E1=H,E2=H,/E3=L, /E4=L). THE PREVIOUS DATA IS HELD IN THE PRIORITY ENCODER REGISTERS IF ANY OF THE ENABLE INPUTS ARE FALSE (E1=L,E2=L,/E3=H,/E4=H) REGARDLESS OF CLOCK TRANSITIONS. NOTE THAT THE POLARITY OF THE ENABLES CAN BE CHANGED BY MERELY EDITING THE LOGIC EQUATIONS. OUTPUT Q4 SERVES AS THE INTERRUPT FLAG AND IS TRUE (Q4=L) WHEN ANY OF THE 8 INPUTS ARE ACTIVE (I=H) ON THE RISING EDGE OF THE CLOCK (CLK) PROVIDING THE FOUR ENABLE INPUTS ARE TRUE (E1=H,E2=H,/E3=L,/E4=L). THE INTERRUPT FLAG IS FALSE (Q4=H) WHEN ALL INPUTS ARE INACTIVE (I=L) OR WHEN ANY ONE OF THE FOUR ENABLE INPUTS ARE FALSE (E1=L,E2=L,/E3=H,/E4=H). OPERATIONS TABLE /OC CLK E1 E2 /E3 /E4 I7-I0 Q4 Q3-Q0 OPERATION ------------------------------------------------------------------------- H X X X X X X Z Z HI-Z L C L X X X X H Q NOT ENABLED (E1=L) L C X L X X X H Q NOT ENABLED (E2=L) L C X X H X X H Q NOT ENABLED (/E3=H) L C X X X H X H Q NOT ENABLED (/E4=H) L C H H L L L H X NO INTERRUPT FLAG L C H H L L I0=H L 7 I0 INTERRUPT (HIGHEST PRIORITY) L C H H L L I1=H L 6 I1 INTERRUPT L C H H L L I1=H L 5 I2 INTERRUPT L C H H L L I1=H L 4 I3 INTERRUPT L C H H L L I1=H L 3 I4 INTERRUPT L C H H L L I1=H L 2 I5 INTERRUPT L C H H L L I1=H L 1 I6 INTERRUPT L C H H L L I1=H L 0 I7 INTERRUPT (LOWEST PRIORITY) -------------------------------------------------------------------------------