PAL16R4                                                PAL DESIGN SPECIFICATION
P7086                                                     VINCENT COLI 05/15/82
SN54/74S508 I/O DEVICE INTERFACE WITH THE INTEL 8085 (DESIGN # 2)
MMI SUNNYVALE, CALIFORNIA
CLK A15 A14 A13 A12 A11 A10 A9 A8 GND
/OE IOM ALE I2  I1  I0  /GO S1 S0 VCC


GO := /A11*/A12*/A13* A14*/A15   ;MONITOR ADDRESS BUS (A11-A15)
    *  IOM*/S1 * S0              ;MONITOR MACHINE CYCLE STATUS (I/O WRITE)
    * /ALE                       ;MONITOR ADDRESS/DATA CONTROL (FALLING EDGE)

/I0 := /A8     ;REGISTER INSTRUCTION INPUT I0

/I1 := /A9     ;REGISTER INSTRUCTION INPUT I1

/I2 := /A10    ;REGISTER INSTRUCTION INPUT I2


FUNCTION TABLE

/OE CLK A8 A9 A10 A11 A12 A13 A14 A15 IOM S1 S0 ALE I0 I1 I2 /GO

;         ADDR BUS   MACH STATUS      INSTR           COMMENTS
;/OE CLK  89012345   IOM S1 S0   ALE  012   /GO   (OCTAL ADDRESS)
-------------------------------------------------------------------------------
  L   C   XXXLLLLH    H  L  H     L   XXX    H    (200 TO 207) INACTIVE
  L   C   XXXLLLLH    H  H  L     L   XXX    H    (100 TO 107) I/O READ
  L   C   XXXLLLHL    H  H  H     L   XXX    H    (100 TO 107) INTERRUPT ACKNOW
  L   C   XXXLLLHL    L  H  H     H   XXX    H    (100 TO 107) INACTIVE (ALE=H)
  L   C   XXXLLLHL    H  L  H     L   XXX    L    (100 TO 107) (ACTIVE RANGE)
  L   C   LHHLLLHL    H  L  H     L   LHH    L    (106) LOAD X
  L   C   LHHLLLHL    H  L  H     H   LHH    H    (106) NOP (ALE=H)
  L   C   LLLLLLHL    H  L  H     L   LLL    L    (100) LOAD Y
  H   X   XXXXXXXX    X  X  X     X   ZZZ    Z    TEST HI-Z
-------------------------------------------------------------------------------


DESCRIPTION

THIS PAL PROVIDES THE DECODE LOGIC FOR INTERFACING THE MMI SN54/74S508, 8-BIT
SEQUENTIAL MULTIPLIER/DIVIDER, WITH THE INTEL 8085 MICROPROCESSOR.  THE PAL16R4
MONITORS THE UPPER 8 BIT ADDRESS BUS (A8-A15), THE ADDRESS LATCH ENABLE (ALE),
AND THE THREE MACHINE CYCLE STATUS LINES (IOM,S1,S0) FROM THE 8085 IN ORDER TO
DECODE AN ACTIVE LOW CHIP-ACTIVATION SIGNAL (/GO) FOR THE 74S508.  THE
INSTRUCTION LINES AND CHIP-ACTIVATION SIGNAL ARE REGISTERED IN ORDER TO INSURE
THAT INSTRUCTION INPUTS WILL NOT CHANGE WHEN THE CLOCK IS LOW (CLK=L).  BY
MONITORING THE MACHINE STATUS CYCLE, THE 74S508 CAN BE ADDRESS MAPPED BY THE
8085 AS IF IT WERE AN I/O DEVICE, THUS NOT USING ANY MEMORY MAP ADDRESS SPACE.
THE MACHINE CYCLE STATUS FROM THE 8085 IS AVAILABLE ON THE FALLING EDGE OF ALE.

FOR THIS PARTICULAR DESIGN, THE THREE INSTRUCTION INPUTS TO THE 74S508 (I0-I2)
ARE ASSIGNED TO THE THREE LSB BITS OF ADDRESS BUS (A8-A10), WHILE THE REMAINING
ADDRESS BITS (A11-A15) ARE DECODED BY THE PAL TO DETERMINE IF THE 74S508 IS
SELECTED.  ALSO, ADDRESS 100 TO 107 IS RESERVED FOR THE 74S508.  THE ADDRESS
SPACE CAN BE CHANGED BY SIMPLY EDITING THE LOGIC EQUATIONS.