PAL16R4                                                PAL DESIGN SPECIFICATION
P7085                                                     VINCENT COLI 05/15/82
SN54/74S508 MEMORY MAP INTERFACE WITH THE INTEL 8085 (DESIGN # 1)
MMI SUNNYVALE, CALIFORNIA
CLK AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND
/OE /E1 ALE I2  I1  I0  /GO E2  E3  VCC


GO := /AD3*/AD4*/AD5* AD6*/AD7    ;MONITOR ADDRESS/DATA BUS (AD3-AD7)
    *  E1 * E2*  E3               ;MONITOR ENABLES (FROM A8-A15)
    *  ALE                        ;MONITOR ADDRESS/DATA CONTROL

/I0 := /AD0    ;REGISTER INSTRUCTION INPUT I0

/I1 := /AD1    ;REGISTER INSTRUCTION INPUT I1

/I2 := /AD2    ;REGISTER INSTRUCTION INPUT I2


FUNCTION TABLE

/OE CLK AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 /E1 E2 E3 ALE I0 I1 I2 /GO

;         A/D BUS    ADD BUS       INSTR           COMMENTS
;/OE CLK  01234567  /E1 E2 E3  ALE  012   /GO   (OCTAL ADDRESS)
-------------------------------------------------------------------------------
  L   C   XXXLLLLH   L  H  H    H   XXX    H    (200 TO 207) INACTIVE
  L   C   XXXLLLLH   H  H  H    H   XXX    H    (100 TO 107) INACTIVE (/E1=H)
  L   C   XXXLLLHL   L  L  L    H   XXX    H    (100 TO 107) INACTIVE (E2,E3=L)
  L   C   XXXLLLHL   L  H  H    L   XXX    H    (100 TO 107) INACTIVE (ALE=L)
  L   C   XXXLLLHL   L  H  H    H   XXX    L    (100 TO 107) (ACTIVE RANGE)
  L   C   LHHLLLHL   L  H  H    H   LHH    L    (106) LOAD X
  L   C   LHHLLLHL   L  H  H    L   LHH    H    (106) NOP (ALE=L)
  L   C   LLLLLLHL   L  H  H    H   LLL    L    (100) LOAD Y
  H   X   XXXXXXXX   X  X  X    X   ZZZ    Z    TEST HI-Z
-------------------------------------------------------------------------------


DESCRIPTION

THIS PAL PROVIDES THE DECODE LOGIC FOR INTERFACING THE MMI SN54/74S508, 8-BIT
SEQUENTIAL MULTIPLIER/DIVIDER, WITH THE INTEL 8085 MICROPROCESSOR.  THE PAL16R4
MONITORS THE LOWER 8 BIT ADDRESS/DATA BUS (AD0-AD7), THE ADDRESS LATCH ENABLE
(ALE), AND THREE OF THE UPPER 8 BIT ADDRESS BUS (A8-A15) WHICH IS LABELED
/E1,E2,E3 FROM THE 8085 IN ORDER TO DECODE AN ACTIVE LOW CHIP-ACTIVATION SIGNAL
(/GO) FOR THE MULTIPLIER/DIVIDER.  THE INSTRUCTION LINES AND CHIP-ACTIVATION
SIGNAL ARE REGISTERED IN ORDER TO INSURE THAT INSTRUCTION INPUTS WILL NOT
CHANGE WHEN THE CLOCK IS LOW (CLK=L).

FOR THIS PARTICULAR DESIGN, THE THREE INSTRUCTION INPUTS TO THE 74S508 (I0-I2)
ARE ASSIGNED TO THE THREE LSB ADDRESS/DATA BUS (AD0-AD2), WHILE THE REMAINING
ADDRESS BITS (AD3-AD7) ARE DECODED BY THE PAL TO DETERMINE IF THE 74S508 IS
SELECTED.  ALSO, ADDRESS 100 TO 107 IS RESERVED FOR THE 74S508.  THE ADDRESS
SPACE CAN BE CHANGE BY EDITING THE LOGIC EQUATIONS.

THIS PAL DESIGN CORRESPONDS TO FIGURE 6 ON PAGE 7 OF THE FOLLOWING APPLICATION
NOTE:

AN-103  "A DEDICATED MULTIPLIER/DIVIDER SPEEDS UP MULTIPLICATION AND DIVISION
         FOR 8-BIT MICROPROCESSORS" by Ehud Gordon