PAL16R8 PAL DESIGN SPECIFICATION P7080 (PMSI002) DANESH TAVANA 04/27/82 OCTAL ADDRESSABLE REGISTER WITH DEMULTIPLEXER/CLEAR MMI SUNNYVALE, CALIFORNIA CLK /CLR /PR A B C MODE /E DIN GND /OC Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC /Q0 := CLR ;CLEAR (LSB) + /PR* E*/MODE*/C*/B*/A ;DEMULTIPLEX OUTPUT /Q0=H + /PR* E* MODE*/C*/B*/A*/DIN ;REGISTER OUTPUT /Q0=/DIN + /PR* E* MODE* A*/Q0 ;LOAD PREVIOUS STATE (/Q0) OR A LOW + /PR* E* MODE* B */Q0 ;LOAD PREVIOUS STATE (/Q0) OR A LOW + /PR* E* MODE* C */Q0 ;LOAD PREVIOUS STATE (/Q0) OR A LOW + /PR*/E */Q0 ;HOLD IF NOT LOADING (/E=H) /Q1 := CLR ;CLEAR + /PR* E*/MODE*/C*/B* A ;DEMULTIPLEX OUTPUT /Q1=H + /PR* E* MODE*/C*/B* A*/DIN ;REGISTER OUTPUT /Q1=/DIN + /PR* E* MODE* /A*/Q1 ;LOAD PREVIOUS STATE (/Q1) OR A LOW + /PR* E* MODE* B */Q1 ;LOAD PREVIOUS STATE (/Q1) OR A LOW + /PR* E* MODE* C */Q1 ;LOAD PREVIOUS STATE (/Q1) OR A LOW + /PR*/E */Q1 ;HOLD IF NOT LOADING (/E=H) /Q2 := CLR ;CLEAR + /PR* E*/MODE*/C* B*/A ;DEMULTIPLEX OUTPUT /Q2=H + /PR* E* MODE*/C* B*/A*/DIN ;REGISTER OUTPUT /Q2=/DIN + /PR* E* MODE* A*/Q2 ;LOAD PREVIOUS STATE (/Q2) OR A LOW + /PR* E* MODE* /B */Q2 ;LOAD PREVIOUS STATE (/Q2) OR A LOW + /PR* E* MODE* C */Q2 ;LOAD PREVIOUS STATE (/Q2) OR A LOW + /PR*/E */Q2 ;HOLD IF NOT LOADING (/E=H) /Q3 := CLR ;CLEAR + /PR* E*/MODE*/C* B* A ;DEMULTIPLEX OUTPUT /Q3=H + /PR* E* MODE*/C* B* A*/DIN ;REGISTER OUTPUT /Q3=/DIN + /PR* E* MODE* /A*/Q3 ;LOAD PREVIOUS STATE (/Q3) OR A LOW + /PR* E* MODE* /B */Q3 ;LOAD PREVIOUS STATE (/Q3) OR A LOW + /PR* E* MODE* C */Q3 ;LOAD PREVIOUS STATE (/Q3) OR A LOW + /PR*/E */Q3 ;HOLD IF NOT LOADING (/E=H) /Q4 := CLR ;CLEAR + /PR* E*/MODE* C*/B*/A ;DEMULTIPLEX OUTPUT /Q4=H + /PR* E* MODE* C*/B*/A*/DIN ;REGISTER OUTPUT /Q4=/DIN + /PR* E* MODE* A*/Q4 ;LOAD PREVIOUS STATE (/Q4) OR A LOW + /PR* E* MODE* B */Q4 ;LOAD PREVIOUS STATE (/Q4) OR A LOW + /PR* E* MODE*/C */Q4 ;LOAD PREVIOUS STATE (/Q4) OR A LOW + /PR*/E */Q4 ;HOLD IF NOT LOADING (/E=H) /Q5 := CLR ;CLEAR + /PR* E*/MODE* C*/B* A ;DEMULTIPLEX OUTPUT /Q5=H + /PR* E* MODE* C*/B* A*/DIN ;REGISTER OUTPUT /Q5=/DIN + /PR* E* MODE* /A*/Q5 ;LOAD PREVIOUS STATE (/Q5) OR A LOW + /PR* E* MODE* B */Q5 ;LOAD PREVIOUS STATE (/Q5) OR A LOW + /PR* E* MODE*/C */Q5 ;LOAD PREVIOUS STATE (/Q5) OR A LOW + /PR*/E */Q5 ;HOLD IF NOT LOADING (/E=H) /Q6 := CLR ;CLEAR + /PR* E*/MODE* C* B*/A ;DEMULTIPLEX OUTPUT /Q6=H + /PR* E* MODE* C* B*/A*/DIN ;REGISTER OUTPUT /Q5=/DIN + /PR* E* MODE* A*/Q6 ;LOAD PREVIOUS STATE (/Q6) OR A LOW + /PR* E* MODE* /B */Q6 ;LOAD PREVIOUS STATE (/Q6) OR A LOW + /PR* E* MODE*/C */Q6 ;LOAD PREVIOUS STATE (/Q6) OR A LOW + /PR*/E */Q6 ;HOLD IF NOT LOADING (/E=H) /Q7 := CLR ;CLEAR (MSB) + /PR* E*/MODE* C* B* A ;DEMULTIPLEX OUTPUT /Q7=H + /PR* E* MODE* C* B* A*/DIN ;REGISTER OUTPUT /Q7=/DIN + /PR* E* MODE* /A*/Q7 ;LOAD PREVIOUS STATE (/Q7) OR A LOW + /PR* E* MODE* /B */Q7 ;LOAD PREVIOUS STATE (/Q7) OR A LOW + /PR* E* MODE*/C */Q7 ;LOAD PREVIOUS STATE (/Q7) OR A LOW + /PR*/E */Q7 ;HOLD IF NOT LOADING (/E=H) FUNCTION TABLE /OC CLK /CLR /PR /E MODE C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 ; ----OUTPUTS---- ;CONTROL ---FUNCTIONS---- -INPUTS-- Q Q Q Q Q Q Q Q ;/OC CLK /CLR /PR /E MODE C B A DIN 7 6 5 4 3 2 1 0 COMMENTS ------------------------------------------------------------------------------- L C L L X X X X X X L L L L L L L L CLEAR (OVERRD /PR) L C H L X X X X X X H H H H H H H H PRESET (OVERRD ENABLES) L C H H L H L L L L H H H H H H H L LOAD Q0 WITH DIN L C H H L H L L H L H H H H H H L L LOAD Q1 WITH DIN L C H H L H L H L L H H H H H L L L LOAD Q2 WITH DIN L C H H L H L H H L H H H H L L L L LOAD Q3 WITH DIN L C H H L H H L L L H H H L L L L L LOAD Q4 WITH DIN L C H H L H H L H L H H L L L L L L LOAD Q5 WITH DIN L C H H L H H H L L H L L L L L L L LOAD Q6 WITH DIN L C H H L H H H H L L L L L L L L L LOAD Q7 WITH DIN L C H H L H H H H H H L L L L L L L LOAD Q7 WITH DIN L C H H L H H H L H H H L L L L L L LOAD Q6 WITH DIN L C H H L H H L H H H H H L L L L L LOAD Q5 WITH DIN L C H H L H H L L H H H H H L L L L LOAD Q4 WITH DIN L C H H L H L H H H H H H H H L L L LOAD Q3 WITH DIN L C H H L H L H L H H H H H H H L L LOAD Q2 WITH DIN L C H H L H L L H H H H H H H H H L LOAD Q1 WITH DIN L C H H L H L L L H H H H H H H H H LOAD Q0 WITH DIN L C H H L L L L L X H H H H H H H L DECODE ADDRESS LINE 0 L C H H L L L L H X H H H H H H L H DECODE ADDRESS LINE 1 L C H H L L L H L X H H H H H L H H DECODE ADDRESS LINE 2 L C H H L L L H H X H H H H L H H H DECODE ADDRESS LINE 3 L C H H L L H L L X H H H L H H H H DECODE ADDRESS LINE 4 L C H H L L H L H X H H L H H H H H DECODE ADDRESS LINE 5 L C H H L L H H L X H L H H H H H H DECODE ADDRESS LINE 6 L C H H L L H H H X L H H H H H H H DECODE ADDRESS LINE 7 L C H H H X X X X X L H H H H H H H HOLD PREVIOUS STATE H X X X X X X X X X Z Z Z Z Z Z Z Z TEST HI-Z ------------------------------------------------------------------------------- DESCRIPTION THE OCTAL ADDRESSABLE REGISTER AND DEMULTIPLEXER PERFORMS ONE OF TWO MSI FUNCTIONS DEPENDING ON THE STATE OF THE MODE SELECT PIN. IF MODE=HIGH THEN THE PART PERFORMS THE FUNCTION OF AN ADDRESSABLE REGISTER WITH 8 OUTPUTS (Q7-Q0) AND ONE DATA INPUT (DIN). THE REGISTERED OUTPUT IS SELECTED BY THREE INPUT ADDRESS PINS (A,B,C). WITH MODE=LOW CONVERTS THIS CHIP INTO AN ACTIVE LOW 3-TO-8 DEMULTIPLEXER, WHERE THE ADDRESSED OUTPUT IS LOW AND ALL OTHER OUTPUTS REMAIN HIGH. CLEAR (/CLR) AND PRESET (/PR) ARE ACTIVE LOW OUTPUTS WHICH SET ALL OUTPUTS TO LOW OR HIGH RESPECTIVELY. WHEN ENABLE (/E) IS HIGH, THE CHIP IS DISABLED AND THE OUTPUTS RETAIN THEIR PREVIOUS STATES. CLEAR OVERRIDES PRESET AND ENABLE, PRESET OVERRIDES ENABLE. THESE FUNCTIONS ARE EXERCISED IN THE FUNCTION TABLE AND SUMMARIZED IN THE OPERATIONS TABLE: /OC CLK /CLR /PR /E MODE C B A DIN Q7-Q0 OPERATION ------------------------------------------------------------------------ H X X X X X X X X X Z HI-Z L C L X X X X X X X L CLEAR L C H L X X X X X X H PRESET L C H H L L C B A X MUX ADDRESSED OUTPUT=LOW L C H H L H C B A DIN REG ADDRESSED OUTPUT=DIN L C H H H X X X X X Q HOLD PREVIOUS STATES ------------------------------------------------------------------------ OUTPUT SELECT TABLE C B A DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 ----------------------------------------------- L L L DIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 DIN L L H DIN Q7 Q6 Q5 Q4 Q3 Q2 DIN Q0 L H L DIN Q7 Q6 Q5 Q4 Q3 DIN Q1 Q0 L H H DIN Q7 Q6 Q5 Q4 DIN Q2 Q1 Q0 H L L DIN Q7 Q6 Q5 DIN Q3 Q2 Q1 Q0 H L H DIN Q7 Q6 DIN Q4 Q3 Q2 Q1 Q0 H H L DIN Q7 DIN Q5 Q4 Q3 Q2 Q1 Q0 H H H DIN DIN Q6 Q5 Q4 Q3 Q2 Q1 Q0 ------------------------------------------------