PAL16R6                                      PAL DESIGN SPECIFICATION
P7065                                           VINCENT COLI 06/10/81
6-BIT SHIFT REGISTER
MMI SUNNYVALE, CALIFORNIA
CLK  I0  D0 D1 D2 D3 D4 D5  I1  GND
/OC RILO Q5 Q4 Q3 Q2 Q1 Q0 LIRO VCC


/Q0 := /I1*/I0*/Q0             ;HOLD Q0
     + /I1* I0*/Q1             ;SHIFT RIGHT
     +  I1*/I0*/LIRO           ;SHIFT LEFT
     +  I1* I0*/D0             ;LOAD D0

/Q1 := /I1*/I0*/Q1             ;HOLD Q1
     + /I1* I0*/Q2             ;SHIFT RIGHT
     +  I1*/I0*/Q0             ;SHIFT LEFT
     +  I1* I0*/D1             ;LOAD D1

/Q2 := /I1*/I0*/Q2             ;HOLD Q2
     + /I1* I0*/Q3             ;SHIFT RIGHT
     +  I1*/I0*/Q1             ;SHIFT LEFT
     +  I1* I0*/D2             ;LOAD D2

/Q3 := /I1*/I0*/Q3             ;HOLD Q3
     + /I1* I0*/Q4             ;SHIFT RIGHT
     +  I1*/I0*/Q2             ;SHIFT LEFT
     +  I1* I0*/D3             ;LOAD D3

/Q4 := /I1*/I0*/Q4             ;HOLD Q4
     + /I1* I0*/Q5             ;SHIFT RIGHT
     +  I1*/I0*/Q3             ;SHIFT LEFT
     +  I1* I0*/D4             ;LOAD Q5

/Q5 := /I1*/I0*/Q5             ;HOLD Q5
     + /I1* I0*/RILO           ;SHIFT RIGHT
     +  I1*/I0*/Q4             ;SHIFT LEFT
     +  I1* I0*/D5             ;LOAD Q5

IF(/I1*I0) /LIRO = /Q0         ;LEFT IN RIGHT OUT

IF(I1*/I0) /RILO = /Q5         ;RIGHT IN LEFT OUT


FUNCTION TABLE

I1 I0 D5 D4 D3 D2 D1 D0 CLK /OC RILO LIRO Q5 Q4 Q3 Q2 Q1 Q0

;        D IN                           Q OUT
;INST   D5--D0   CLK   /OC  RILO  LIRO  Q5--Q0   COMMENTS
-------------------------------------------------------------------
 HH     LLLLLL    C     L    Z     Z    LLLLLL   LOAD ZEROS
 LL     XXXXXX    C     L    Z     Z    LLLLLL   HOLD
 HL     XXXXXX    C     L    L     H    LLLLLH   SHIFT LEFT IN A H
 HL     XXXXXX    C     L    L     L    LLLLHL   SHIFT LEFT IN A L
 HL     XXXXXX    C     L    L     L    LLLHLL   SHIFT LEFT IN A L
 HL     XXXXXX    C     L    L     L    LLHLLL   SHIFT LEFT IN A L
 HL     XXXXXX    C     L    L     L    LHLLLL   SHIFT LEFT IN A L
 HL     XXXXXX    C     L    H     L    HLLLLL   SHIFT LEFT IN A L
 HL     XXXXXX    C     L    L     L    LLLLLL   SHIFT LEFT IN A L
 LL     XXXXXX    X     H    Z     Z    ZZZZZZ   TEST HI-Z
 HH     HHHHHH    C     L    Z     Z    HHHHHH   LOAD ONES
 LL     XXXXXX    C     L    Z     Z    HHHHHH   HOLD
 LH     XXXXXX    C     L    L     H    LHHHHH   SHIFT RIGHT IN A L
 LH     XXXXXX    C     L    H     H    HLHHHH   SHIFT RIGHT IN A H
 LH     XXXXXX    C     L    H     H    HHLHHH   SHIFT RIGHT IN A H
 LH     XXXXXX    C     L    H     H    HHHLHH   SHIFT RIGHT IN A H
 LH     XXXXXX    C     L    H     H    HHHHLH   SHIFT RIGHT IN A H
 LH     XXXXXX    C     L    H     L    HHHHHL   SHIFT RIGHT IN A H
 LH     XXXXXX    C     L    H     H    HHHHHH   SHIFT RIGHT IN A H
 LL     XXXXXX    X     H    Z     Z    ZZZZZZ   TEST HI-Z
-------------------------------------------------------------------


DESCRIPTION

THIS PAL IS A 6-BIT SHIFT REGISTER WITH PARALLEL LOAD AND HOLD CAPABILITY.
TWO FUNCTION SELECT INPUT (I0,I1) PROVIDE ONE OF FOUR OPERATIONS WHICH OCCUR
SYNCHRONOUSLY ON THE RISING EDGE OF THE CLOCK (CLK).  THESE OPERATIONS ARE:

      /OC  CLK  I1  I0  D5-D0  Q5-Q0    OPERATION
      ----------------------------------------------
       H    X   X   X     X      Z      HI-Z
       L    C   L   L     X      L      HOLD
       L    C   L   H     X    SR(Q)    SHIFT RIGHT
       L    C   H   L     D    SL(Q)    SHIFT LEFT
       L    C   H   H     D      D      LOAD
      ----------------------------------------------

TWO OR MORE 6-BIT SHIFT REGISTERS MAY BE CASCADED TO PROVIDE LARGER SHIFT
REGISTERS.  RILO AND LIRO ARE LOCATED ON PINS 12 AND 19 RESPECTIVELY, WHICH
PROVIDES FOR CONVENIENT INTERCONNECTIONS WHEN TWO OR MORE 6-BIT SHIFT REGISTERS
ARE CASCADED TO IMPLEMENT LARGER SHIFT REGISTERS.