PAL16R8 PAL DESIGN SPECIFICATION P7013 VINCENT COLI 07/12/82 SN54/74S516 (16-BIT MULTIPLIER/DIVIDER/ACCUMULATOR CO-PROCESSOR) STATE COUNTER MMI SUNNYVALE, CALIFORNIA CK I0 I1 I2 /GO /MODE INIT SET8 SET10 GND /OE Q3 Q2 Q1 Q0 /D /C /B /A VCC ; STATE COUNTER LOGIC EQUATIONS A := /INIT* D* C * A ;DECODE STATE 13 OR 15 + /INIT * C*/B* A ;DECODE STATE 5 OR 13 + /INIT*/D*/C * I2*/I1* I0* GO ;DECODE STATE 0, 1, 3, OR 11 + /INIT */C * A* I2*/I1* I0* GO ;AND INSTRUCTION 5 AND /GO=L + /INIT */C * A */GO ;HOLD A IF STATE 1, 3, 11 AND /GO=H + /INIT */C * I2 */I0* GO ;DECODE STATE 0,1,3,8,10,11 INST 4,6 B := /INIT* D* C*/B* A* Q3* Q2* Q1 ;DECODE STATE 13 (DIVIDE LOOP) + /INIT * C* B ;DECODE STATE 6, 7, 14, OR 15 + /INIT*/D*/C * A* I2* I1*/I0* GO ;DECODE STATE 1 OR 3, INSTR 6, /GO=L + /INIT */C * B */GO ;HOLD B IF STATE 3, 10, 11 AND /GO=H + INIT* SET10 ;SET STATE 10 IF INIT=H AND SET10=H C := /INIT* D* C*/B*/A*/Q3 ;DECODE STATE 12 (MULTIPLY LOOP) + /INIT*/D* C ;DECODE STATE 4, 5, 6, OR 7 + /INIT * C * A ;DECODE STATE 5, 7, 13, OR 15 + /INIT */C * A* I2*/I1 * GO ;DECODE STATE 1,3,11, INST 4,5 /GO=L + /INIT */C */I2 * GO ;DECODE STATE 0, 1, 3, 8, 10, OR 11 + /INIT */C */I1*/I0* GO ;AND INST 0, 1, 2, 3, OR 4 AND /GO=L D := /INIT * C*/B ;DECODE STATE 4, 5, 12, OR 13 + /INIT * C */A ;DECODE STATE 4, 6, 12, OR 14 + /INIT*/D*/C* B* A* I2* I1*/I0* GO ;DECODE STATE 3 AND INST 6 AND /GO=L + /INIT* D*/C */GO ;HOLD D IF STATE 8, 10, 11 AND /GO=H + INIT* SET8 ;SET STATE 8 IF INIT=H AND SET8=H + INIT* SET10 ;SET STATE 10 IF INIT=H AND SET10=H ; MULTIPLY/DIVIDE LOOP LOGIC EQUATIONS /Q0 := /INIT */C * A */Q0 ;HOLD Q0 IF STATE 1, 3, OR 11 + /INIT*/D* C*/B* A* MODE */Q0 ;HOLD IF STATE 5 AND /MODE=L + /INIT* D* C*/B * Q0 ;COUNT IF STATE 12 OR 13 + /INIT*/D* C*/B*/A ;CLEAR Q0 IF STATE 4 + /INIT* D*/C */A ;CLEAR Q0 IF STATE 8 OR 10 + /INIT * C* B ;CLEAR Q0 IF STATE 6, 7, 14,OR 15 + /INIT*/D*/C*/B*/A */I0 ;SET Q0=H IF STATE 0 + /INIT*/D*/C*/B*/A */I2 ;AND INSTRUCTION 5 (OR 7) /Q1 := D* C*/B */Q1*/Q0 ;HOLD IF STATE 12 OR 13 AND Q0=L + D* C*/B * Q1* Q0 ;COUNT IF STATE 12 OR 13 + /D * A ; CLEAR Q1 IF STATE + /C ;0, 1, 3, 5, 6, 7, 8, + B ; 10, 11, 14, OR 15 + INIT ;INITIALIZE Q1 /Q2 := /Q2 */Q0 ;HOLD IF Q0=L + /Q2*/Q1 ;HOLD IF Q1=L + D* C*/B * Q2* Q1* Q0 ;COUNT IF STATE 12 OR 13 + /D ; CLEAR Q2 IF STATE + /C ;0, 1, 3, 4, 5, 6, 7, + B ;8, 10, 11, 14, OR 15 + INIT ;INITIALIZE Q2 /Q3 := /Q3 */Q0 ;HOLD IF Q0=L + /Q3 */Q1 ;HOLD IF Q1=L + /Q3*/Q2 ;HOLD IF Q2=L + D* C*/B * Q3* Q2* Q1* Q0 ;COUNT IF STATE 12 OR 13 + /D ; CLEAR Q3 IF STATE + /C ;0, 1, 3, 4, 5, 6, 7, + B ;8, 10, 11, 14, OR 15 + INIT ;INITIALIZE Q3 FUNCTION TABLE CK /OE INIT SET8 SET10 /MODE /GO I2 I1 I0 Q3 Q2 Q1 Q0 D C B A ;CHIP CONTROL SET INSTRUCTIONS QQQQ STATE ;CK /OE INIT 8 10 /MODE /GO I2 I1 I0 3210 D C B A COMMENTS (INSTR-STATE) ------------------------------------------------------------------------------- C L H L L X X X X X LLLH L L L L INITIALIZE (X - 0) C L L L L L L H L H LLLH L L L H LOAD X (FRACT) (5 - 1) C L L L L L L L X X LLLH L H L L LOAD Y (0,1,2,3 - 4) C L L L L L L X X X LLHL H H L L MULT LOOP 1 XY (X -12) C L L L L L L X X X LLHH H H L L MULT LOOP 2 XY (X -12) C L L L L L L X X X LHLL H H L L MULT LOOP 3 XY (X -12) C L L L L L L X X X LHLH H H L L MULT LOOP 4 XY (X -12) C L L L L L L X X X LHHL H H L L MULT LOOP 5 XY (X -12) C L L L L L L X X X LHHH H H L L MULT LOOP 6 XY (X -12) C L L L L L L X X X HLLL H H L L MULT LOOP 7 XY (X -12) C L L L L L L X X X HLLH H L L L MULT(EXIT LOOP)(X - 8) C L L L L L L H L H LLLL L L L L ROUND Z,W (5 - 0) C L L L L L L H H H LLLH L L L L READ Z (7 - 0) C L L L L L L H L H LLLH L L L H LOAD X (FRACT) (5 - 1) C L L L L L L H H L LLLH L L H H LOAD Z (6 - 3) C L L L L L L H L L LLLH L H L H LOAD W (4 - 5) C L L L L L L X X X LLLH H H L H DIVIDE LOOP 1 (X -13) C L L L L L L X X X LLHL H H L H DIVIDE LOOP 2 (X -13) C L L L L L L X X X LLHH H H L H DIVIDE LOOP 3 (X -13) C L L L L L L X X X LHLL H H L H DIVIDE LOOP 4 (X -13) C L L L L L L X X X LHLH H H L H DIVIDE LOOP 5 (X -13) C L L L L L L X X X LHHL H H L H DIVIDE LOOP 6 (X -13) C L L L L L L X X X LHHH H H L H DIVIDE LOOP 7 (X -13) C L L L L L L X X X HLLL H H L H DIVIDE LOOP 8 (X -13) C L L L L L L X X X HLLH H H L H DIVIDE LOOP 9 (X -13) C L L L L L L X X X HLHL H H L H DIVIDE LOOP 10 (X -13) C L L L L L L X X X HLHH H H L H DIVIDE LOOP 11 (X -13) C L L L L L L X X X HHLL H H L H DIVIDE LOOP 12 (X -13) C L L L L L L X X X HHLH H H L H DIVIDE LOOP 13 (X -13) C L L L L L L X X X HHHL H H L H DIVIDE LOOP 14 (X -13) C L L L L L L X X X HHHH H H H H DIV(EXIT LOOP) (X -15) C L L L L L L X X X LLLL L H H H DIVIDE Z,W/X (X - 7) C L L L L L L X X X LLLL L H H L DIVIDE Z,W/X (X - 6) C L L L L L L X X X LLLL H H H L DIVIDE Z,W/X (X -14) C L L L L L L X X X LLLL H L H L DIVIDE Z,W/X (X -10) C L L L L L L H H H LLLL L L L L READ Z (QUOT) (7 - 0) C L L L L L L H H H LLLH L L L L READ W (REM) (7 - 0) C L L L L L L H L H LLLH L L L H ROUND Z (5 - 1) C L L L L L L H H H LLLH L L L L READ Z (QUOT) (7 - 0) C L L L L L L H L H LLLH L L L H LOAD X (FRACT) (5 - 1) C L L L L L L H H L LLLH L L H H LOAD Z (6 - 3) C L L L L L L H H L LLLH H L H H LOAD W (6 -11) C L L L L L L H H H LLLH L L L L CLEAR Z (7 - 0) C L L L L L L H H L LLLL L L L H LOAD X(INTEGER)(6 - 1) C L L L L L L H L H LLLL L H L H DIVIDE Kz/X (5 - 5) C L L L L L L X X X LLLL H H L H DIVIDE LOOP 1 (X -13) C L L L L L L X X X LLLH H H L H DIVIDE LOOP 2 (X -13) C L H L L X X X X X LLLH L L L L INITIALIZE (X - 0) C L L L L L L H H L LLLL L L L H LOAD X(INTEGER)(6 - 1) C L L L L L L H H L LLLL L L H H LOAD Z (6 - 3) C L L L L L L H H H LLLL L L L L READ Z (7 - 0) C L L L L L L H L H LLLH L L L H LOAD X (FRACT) (5 - 1) C L L L L L L H H L LLLH L L H H LOAD Z (6 - 3) C L L L L L L H H L LLLH H L H H LOAD Wsign (6 -11) C L L L L L L H H L LLLH L L L H INCOMPLETE OPER(6 - 1) C L L L L L L H H L LLLH L L H H LOAD Z (6 - 3) C L L L L L L H H L LLLH H L H H LOAD Wsign (6 -11) C L L L L L L H L L LLLH L H L H DIVIDE Wsign/X (4 - 5) C L H L L L L X X X LLLH L L L L INITIALIZE (X - 0) C L L L L L L L X X LLLL L H L L LOAD Y (0,1,2,3 - 4) C L H L L L L X X X LLLH L L L L INITIALIZE (X - 0) C L L L L L L H L L LLLL L H L H DIVIDE Kz,Kw/X1(4 - 5) C L H H L L L X X X LLLH H L L L SET TO STATE 8 (X - 8) C L L L L L L L X X LLLL L H L L LOAD Y (0,1,2,3 - 4) C L H H L L L X X X LLLH H L L L SET TO STATE 8 (X - 8) C L L L L L L H L L LLLL L H L H DIVIDE Kz,Kw/X1(4 - 5) C L H H L L L X X X LLLH H L L L SET TO STATE 8 (X - 8) C L L L L L L H H L LLLL L L L H LOAD X (6 - 1) C L L L L L L H H L LLLL L L H H LOAD Z (6 - 3) C L L L L L L L X X LLLL L H L L LOAD Y (0,1,2,3 - 4) C L H L H L L X X X LLLH H L H L SET TO STATE 10(X -10) C L L L L L L L X X LLLL L H L L LOAD Y (0,1,2,3 - 4) C L H L H L L X X X LLLH H L H L SET TO STATE 10(X -10) C L L L L L L H L L LLLL L H L H DIVIDE Kz,Kw/X1(4 - 5) C L H L H L L X X X LLLH H L H L SET TO STATE 10(X -10) C L L L L L L H H L LLLL L L L H LOAD X (6 - 1) C L L L L L L H H L LLLL L L H H LOAD Z (6 - 3) C L L L L L L H H L LLLL H L H H LOAD W (6 -11) C L L L L L L L X X LLLL L H L L LOAD Y (0,1,2,3 - 4) X H X X X X X X X X ZZZZ Z Z Z Z TEST HI-Z ------------------------------------------------------------------------------- DESCRIPTION THIS PAL TRACKS ALL 14 OF THE VALID STATE TRANSITIONS FOR THE SN54/74S516, 16-BIT SEQUENTIAL MULTIPLIER/DIVIDER/ACCUMULATOR. THE PAL MONITORS THE 3-BIT INSTRUCTION LINE (I2-I0) AND CHIP ACTIVATION INPUT (/GO) TO THE 'S516 IN ORDER TO PROVIDE THE 4-BIT STATE OF THE MACHINE (D,C,B,A) SYNCHRONOUS WITH THE '516 CLOCK (CK). THE PAL IS INITIALIZED TO STATE 0 BY DRIVING INIT HIGH (INIT=H) FOLLOWED BY A CLOCK PULSE. HOWEVER IN A SYSTEM WITH THE 'S516, THE PAL CAN BE INITIALIZED TO STATE 0 ALONG WITH THE 'S516 BY RECEIVING 23 CLOCK PULSES WITH INSTRUCTION CODE 7. IN ADDITION TO THE INITIALIZATION PIN (INIT), TWO OTHER PINS ARE INCLUDED TO MAKE IT EASIER TO FUNCTIONAL TEST THE DEVICE: SET8 - WHEN SET8=HIGH, THE MACHINE WILL BE SET TO STATE 8 SET10 - WHEN SET10=HIGH, THE MACHINE WILL BE SET TO STATE 10 NOTICE THAT INIT, SET8, AND SET10 CAN BE CONVENIENTLY TIED TO GROUND FOR NORMAL CIRCUIT OPERATION. ALSO SET10 OVERRIDES SET8. OPERATIONS TABLE FOR THE 'S516 STATE COUNTER: /OE CK INIT /MODE /GO I2-I0 /D-/A OPERATION ---------------------------------------------------------------------------- H X X X X X Z HI-Z L C H X X X H INITIALIZATION L C L L X X X FRACTIONAL ARITHMETIC MODE * L C L H X X X INTEGER ARITHMETIC MODE * L C L X H X S HOLD STATE 0, 1, 3, 8, 10, OR 11 L C L X L I S+ STATE TRANSITION ---------------------------------------------------------------------------- * THIS PAL TRACKS THE 'S516 EXACTLY UNDER ALL CONDITIONS EXCEPT WHEN CHAINED INTEGER DIVSION IS TO BE PERFORMED. IN THIS CASE, THE /MODE PIN IS CONNECTED TO AN EXTERNAL REGISTER WHICH IS SET WHEN THE 'S516 PASSES THROUGH STATE 1 WITH INSTRUCTION CODE 6 AND CLEARED WHEN THE 'S516 PASSES THROUGH STATE 1 WITH INSTRUCTION CODE 5. IF YOU DO NOT REQUIRE CHAINED INTEGER DIVISION, THEN SIMPLY CONNECT THE /MODE PIN TO GROUND AND THE PAL STATE COUNTER WILL AUTOMATICALLY KEEP TRACK OF THE REQUIRED NUMBER OF DIVISION LOOPS FOR THE INTEGER AND FRACTIONAL MODES. CONSULT THE SN54/74S516 DATA SHEET FOR MORE INFORMATION ON THE INTEGER AND FRACTIONAL ARITHMETIC MODES.