PAL16R4                                           PAL DESIGN SPECIFICATION
P7010                                                VINCENT COLI 06/28/81
8-BIT I/O PRIORITY INTERRUPT ENCODER WITH REGISTERS
MMI SUNNYVALE, CALIFORNIA
CLK I1 I2 I3 I4 I5 I6 I7 I8 GND
/OC NC NC Q4 Q3 Q2 Q1 NC NC VCC


/Q1 := /I1* I2
     + /I1*/I2*/I3* I4
     + /I1*/I2*/I3*/I4*/I5* I6
     + /I1*/I2*/I3*/I4*/I5*/I6*/I7* I8

/Q2 := /I1*/I2* I3
     + /I1*/I2*/I3* I4
     + /I1*/I2*/I3*/I4*/I5*/I6* I7
     + /I1*/I2*/I3*/I4*/I5*/I6*/I7* I8

/Q3 := /I1*/I2*/I3*/I4* I5
     + /I1*/I2*/I3*/I4*/I5* I6
     + /I1*/I2*/I3*/I4*/I5*/I6* I7
     + /I1*/I2*/I3*/I4*/I5*/I6*/I7* I8

/Q4 := I1 + I2 + I3 + I4 + I5 + I6 + I7 + I8   ;INTERRUPT FLAG


FUNCTION TABLE

I8 I7 I6 I5 I4 I3 I2 I1 CLK /OC Q4 Q3 Q2 Q1

;-INPUTS-   CONTROL   OUTPUTS   COMMENTS
;IIIIIIII   CLK /OC    QQQQ
;87654321              4321
-----------------------------------------------------------------------
 LXXXXXXH    C   L     LHHH     I1 INTERRUPT (HIGHEST PRIORITY DEVICE)
 LXXXXXHL    C   L     LHHL     I2 INTERRUPT
 LXXXXHLL    C   L     LHLH     I3 INTERRUPT
 LXXXHLLL    C   L     LHLL     I4 INTERRUPT
 LXXHLLLL    C   L     LLHH     I5 INTERRUPT
 LXHLLLLL    C   L     LLHL     I6 INTERRUPT
 LHLLLLLL    C   L     LLLH     I7 INTERRUPT
 HLLLLLLL    C   L     LLLL     I8 INTERRUPT (LOWEST PRIORITY DEVICE)
 LLLLLLLL    C   L     HHHH     INTERRUPT FLAG
 XXXXXXXX    X   H     ZZZZ     TEST HI-Z
-----------------------------------------------------------------------


DESCRIPTION

THE I/O PRIORITY INTERRUPT ENCODER PRIORITIZES 8 I/O LINES (I1 THRU I8)
PRODUCING 111 (Q3, Q2, AND Q1 RESPECTIVELY) FOR THE HIGHEST PRIORITY I/O
DEVICE (I1) AND 000 FOR AN INTERRUPT FROM THE LOWEST PRIORITY I/O DEVICE (I8).

OUTPUT Q4 SERVES AS THE INTERRUPT FLAG AND GOES LOW WHEN ANY OF THE 8 I/O
INPUTS GO HIGH.

THE PRIORITY INTERRUPT ENCODER REGISTERS ARE UPDATED ON THE RISING EDGE OF
THE INTERRUPT CLOCK INPUT (CLK).  THE 3-STATE OUTPUTS ARE HIGH-Z WHEN THE
OUTPUT CONTROL LINE (/OC) IS LOW.