OV186.# OVERLAY_ONEOVERLAY_ONE_DS??SEG 8 ,$ pI ERRFLGEXBLKTSTTBLPACKET_DATA_ADDRESSPACKET_DATA_LENGTH TRANSMIT_MODE WAKE_UP_PORT XMT_MDS_DATAXMT_MDS_ADDRESSXMT_MDS_LENGTH RCV_MDS_DATARCV_MDS_ADDRESSRCV_MDS_LENGTH I_TRANSMIT SELF_ADDRESSED PROMISC_PACKET SPECIFIC_PACKET  BAD_VERIFYSEND XMT_CS_WAITXMTTING BAD_TRANSMIT BAD_RECEIVELISTEN RCV_CS_WAITRESP_CONTROLLERSETHERIDS) INT_0_FLAG INT_1_FLAG INT_2_FLAG INT_3_FLAG INT_4_FLAG INT_5_FLAG INT_6_FLAG INT_7_FLAG RCV_INT_FLAGPACKETS_TRANSMITTEDPACKETS_RECEIVED TEST_NUMBER SERDES_MODEPAPBPCܐ9 INTERRUPT INIT_CHIPSu BLOCK_MOVE  SAV_STATUS RESTORE_REGSSET_EXTERNAL_IOSET_INTERNAL_IOINIT_INTERRUPT_VECWAIT_FOR_INT_0WAIT_FOR_INT_1WAIT_FOR_INT_2WAIT_FOR_INT_3WAIT_FOR_INT_4WAIT_FOR_INT_54WAIT_FOR_INT_6FWAIT_FOR_INT_7X READ_ADDRESS.VERIFYP RANDOM_VERIFY APPEND_CRCADDRESS_THE_PACKET FILL_PACKETO RESET_FOR_XMTxTRANSMIT SEND_PACKET XMT_PACKET INIT_8237_XMTINIT_8237_VERIFYINITIALIZE_RECEIVEINSERT_SRC_ADDRSET_UP_CH1_2_3_RCVCLR_REQWAIT_FOR_INT_REQjWAIT_FOR_VERIFY_COMPLETE>MARCHFIND_JUMP_TABLE4EXECUTE_FIRMWAREKWASTE_20_SECONDS RCV_INT_WAITRCV_FLAG_RESETINSERT_DEST_ADDRCHECK_FOR_RCV_INT PREPARE_RCV CHECK_FOR_RCVEXAMINE_PACKETMOVE_RCV_DATA_TO_HOST+ STATION_SYNC; 2OV1860ASM86 VER V3.0 BAD_MOVE~ BASE_8259 BIT_CHANGEے CH_1_AVAILg CH_2_AVAILe CH_3_AVAILc CH0_ADDR_8237"CH0_COUNT_8237 CH1_ADDR_8237CH1_COUNT_8237 CH2_ADDR_8237CH2_COUNT_8237 CH3_ADDR_8237CH3_COUNT_8237 CHANNEL_0_TC6 CHANNEL_1_TCSܒ CHANNEL_2_TC CHANNEL_3_TC< CHANNEL1 CHANNEL2x CHECK_0_TC_OFFX4 CHECK_1_TC_OFFu CHECK_2_TC_OFFǒ CHECK_3_TC_OFFv CHECK_INT_0_OFF_ؒ CHECK_INT_1_OFF CHECK_INT_2_OFF8 CNT_0_8253ے CNT_1_8253ْ CNT_2_8253ג CNTL_8255  COMMAND_8237R CONTINUE_8088r CONTINUE_8237t CREATE_BIT_ERRORS CS_RESET_0 CS_RESET_1( CS_VERIFYђDIAG_TEST_PACKETP)DIAGNOSTIC_MULTICASTM DMA1&3 DMA2'1 DMA3(/ DRAM_GAP_TEST_SPOTd DRAM_SYS_LOCݒECHO_CMD ECHO_REPLY = ENABLE_TXD_WAITp ENABLE_TXD_WAIT2b ENABLE_TXD_WAIT3B ENABLE_TXD_WAIT4EOI_CMD &ETHERNETADDRESSLENGTH EXTRAPOSTPACKETBYTES-EXTRAPREPACKETBYTES FAILA FAIL_8088 FAIL_8237xFALSE FLAG_WAITDÒ GAP_BEGINQ GAP_ENDʒ GAP_TESTx HLDA_0_TEST HLDA_1_TEST HLDA_WAIT] INT_3_OFFB INTEL_NET_IDPM INTERRUPT_1Ғ INTERRUPT_2 INTERRUPT_31 LOOP_CHECK  MASK_8237$ MASK_8259 MB_INT_MASK MBUS_SYS_LOCڒMINIMUM_LENGTH<ϒMINIMUM_LENGTH_RECEIVECV MODE_8237/ MODE_8253) MODE_8255b MULTIBUS_GAP_TEST_SPOTh@ NO_ENABLE_TXD PASS% POLL_8259_CMD  PORT_A_8255V PORT_B_8255T PORT_C_8255RRCV_0_BLOCK_STARTRCV_1_BLOCK_STARTRCV_2_BLOCK_STARTRCV_ACK< RCV_BLOCKSIZETRCV_ID REPORT_ERRORD REQUEST_8237' RESET_8237͒ RESET_CH_CNTRA RESET_ERRS-RESET_MBUS_INTU RESET_TXSTART- RESET_TXSTRT_TEST SET_MBUS_INT SET_TXSTARTɒ SRAM_8088T SRAM_8237"- SRAM_INITIALIZE% STATUS_8237o STOP_ENABLE_TXD~SYNC_PACKET_LENGTHC TABLE TEMP_8237 TEST_8088_EXITԒ TEST_8237_MOVEo3 TEST_88_MOVEu TEST_88_SRAM5 TEST_88_SRAM_0 TEST12P TEST12_EXIT TEST13A TEST13A_EXIT%  TEST13B& TEST13B_EXITdʒ TEST14k TEST14_EXIT TEST15S TEST15_EXIT TEST16+ TEST16_EXIT86 TEST189֒ TEST1Bl TEST1CA TEST1CA_EXITMВ TEST1CBNq TRUE WAIT_LOOP4XMT_ACK,XMT_ACK_PACKET<XMT_BLOCK_START~XMT_CMD XMT_DEST_ADDR0XMT_IDo XMT_ID_PACKET6XMT_RCV_ACK_PACKETXMT_RCV_ID_PACKETxl XMT_SRC_ADDRtXMT_TYPE ,  & k   9 l  N  2°°ðð˾Ã>t.ù&$E&&:uF62&2䣯E&t#NO6&2䣭&2䣯FG3U${C$i˿K <tK <tK <t˚  Ȱ .  >u$u >t$t .  >u$u >t$t.  >u$u >t$t  >u$u >t$t ˚ $uᚁ $$tᚁ $P$t˚ $u$t˚ . $uq $t $u$t  P > 0  . j   ϰ .>d.6h.d ˰ˋ&І€ u &C&&Ú  &&P > $ t˚  P > 6@