OV086/% OVERLAY_ZEROOVERLAY_ZERO_DS??SEGP 8 N  ERRFLGEXBLKTSTTBLPACKET_DATA_ADDRESSPACKET_DATA_LENGTH TRANSMIT_MODE WAKE_UP_PORT XMT_MDS_DATAXMT_MDS_ADDRESSXMT_MDS_LENGTH RCV_MDS_DATARCV_MDS_ADDRESSRCV_MDS_LENGTH I_TRANSMIT SELF_ADDRESSED PROMISC_PACKET SPECIFIC_PACKET  BAD_VERIFYSEND XMT_CS_WAITXMTTING BAD_TRANSMIT BAD_RECEIVELISTEN RCV_CS_WAITRESP_CONTROLLERSETHERIDS) INT_0_FLAG INT_1_FLAG INT_2_FLAG INT_3_FLAG INT_4_FLAG INT_5_FLAG INT_6_FLAG INT_7_FLAG RCV_INT_FLAGPACKETS_TRANSMITTEDPACKETS_RECEIVED TEST_NUMBER SERDES_MODEPAPBPCܐ9 INTERRUPT INIT_CHIPSu BLOCK_MOVE  SAV_STATUS RESTORE_REGSSET_EXTERNAL_IOSET_INTERNAL_IOINIT_INTERRUPT_VECWAIT_FOR_INT_0WAIT_FOR_INT_1WAIT_FOR_INT_2WAIT_FOR_INT_3WAIT_FOR_INT_4WAIT_FOR_INT_54WAIT_FOR_INT_6FWAIT_FOR_INT_7X READ_ADDRESS.VERIFYP RANDOM_VERIFY APPEND_CRCADDRESS_THE_PACKET FILL_PACKETO RESET_FOR_XMTxTRANSMIT SEND_PACKET XMT_PACKET INIT_8237_XMTINIT_8237_VERIFYINITIALIZE_RECEIVEINSERT_SRC_ADDRSET_UP_CH1_2_3_RCVCLR_REQWAIT_FOR_INT_REQjWAIT_FOR_VERIFY_COMPLETE>MARCHFIND_JUMP_TABLE4EXECUTE_FIRMWAREKWASTE_20_SECONDS RCV_INT_WAITRCV_FLAG_RESETINSERT_DEST_ADDRCHECK_FOR_RCV_INT PREPARE_RCV CHECK_FOR_RCVEXAMINE_PACKETMOVE_RCV_DATA_TO_HOST+ STATION_SYNC; 2OV0861ASM86 VER V3.0 BAD_REFRESHp BASE_8259 CH_1_AVAILg CH_2_AVAILe CH_3_AVAILc CH0_ADDR_8237"CH0_COUNT_8237 CH1_ADDR_8237CH1_COUNT_8237 CH2_ADDR_8237CH2_COUNT_8237 CH3_ADDR_8237CH3_COUNT_8237 CHANNEL_SET_UPޒ CHECK_8255E CHECK_IO_LATCHQJ CHECK_SRAM& CHECK_SRAM_INIT CNT_0_8253ے CNT_1_8253ْ CNT_2_8253ג CNTL_8255  COMMAND_8237R COMPAREkR COPYRT COUNT 4 COUNTER_1 COUNTER_2DIAG_TEST_PACKETP)DIAGNOSTIC_MULTICASTM DMA1&3 DMA2'1 DMA3(/ DRAM_CHECKez DRAM_READ_BLOCKo DRAM_SYS_LOCݒECHO_CMD ECHO_REPLY =EOI_CMD &ETHERNETADDRESSLENGTH EXTRAPOSTPACKETBYTES-EXTRAPREPACKETBYTES FAILAFALSE FILL_DRAMV’ FILL_HALF_SRAM@A FINISH_WAITؒ FLY_TEST_0NX FLY_TEST_1 FLY_TEST_2.u INT_5_OFF8В INT_6_OFF_ INT_7_OFF INTEL_NET_IDPM MASK_8237$ MASK_8259 MB_INT_MASK MBUS_IO_BLOCK MBUS_SYS_LOCڒMINIMUM_LENGTH<ϒMINIMUM_LENGTH_RECEIVECV MODE_8237/ MODE_8253) MODE_8255b MOVE_DATA| MOVE_DATA_LOOPԒ MOVE_WAIT{x NEG_DRAMY NEXT_BYTEl OK_REGo PASS% POLL_8259_CMD  PORT_A_8255V PORT_B_8255T PORT_C_8255R PORT_C_LOW ~RCV_0_BLOCK_STARTRCV_1_BLOCK_STARTRCV_2_BLOCK_STARTRCV_ACK< RCV_BLOCKSIZETRCV_ID READ_MULTIBUSD REQUEST_8237' RESET_8237͒ RESET_CH_CNTRA RESET_ERRS-RESET_MBUS_INTU RESET_TXSTART- SET_MBUS_INT SET_TXSTARTɒ SRAM_FILL5В STATUS_8237o STOP_DEAD_0l STOP_DEAD_1 STOP_DEAD_2L,SYNC_PACKET_LENGTHC T11_ERRORs T1EXIT T2B_EXITa TABLE TEMP_8237 TEST_4_EXIT TEST_8237_REG TEST_CHANNELs TEST_D_EXITT TEST_E_EXIT, TEST_F_EXITjԒ TEST_MODE_8237  TEST_PORT_CI TEST_RESET TEST1\ TEST10  TEST10A ֒ TEST10B0 TEST10B_EXIT$ TEST11% TEST11_EXIT TEST11A  TEST2A  TEST2B9ޒ TEST3b TEST4}ܒ TEST6AR TEST6BF TEST8s TEST9K TESTA TESTC TESTD TESTEK TESTF. TRUE WAIT_FOR_GO WAIT_FOR_RESET8& WAIT_TO_GOʒXMT_ACK,XMT_ACK_PACKET<XMT_BLOCK_START~XMT_CMD XMT_DEST_ADDR0XMT_IDo XMT_ID_PACKET6XMT_RCV_ACK_PACKETXMT_RCV_ID_PACKETxl XMT_SRC_ADDRtXMT_TYPE L  9 b }  K        %  u (c) intel corp 1981z $u$t˚ Zɚ <u&&3&rGGˋ36>&6>&KuÃ>u˃>u˅   @3&3&G3ظ ` 怚  ˸@3 @3&:uC˃>t ߹@3@3ۚ ˹ 3 3ۚ ˸&P#&3&X&;t  :ðtt˚ Ӱ2К4 >u0Ӛ4 >t2ЊЊu0ЊЊЊЊ;t`Ӱ*њF >upӚF >t2ъъupъъъъ;tӰ:ҚX >uӚX >t2ҊҊuҊҊҊҊ;tˆ;tΉ΃ÃÊ"ˋװ . . $ . . !3ۋ.  0. {. $ ɻcZǹȳZ#ŠÊĊŊƊNJ. H˰ṩ. I. J . K &iȰHˋ. E