;/********************************************************************
;*                                                                   *
;*    Copyright 1988 Intel Corporation, all rights reserved.         *
;*                                                                   *
;*           INTEL CORPORATION PROPRIETARY INFORMATION               *
;*                                                                   *
;*      This software is supplied under the terms of a license       *
;*      agreement or nondisclosure agreement with Intel Corpo-       *
;*      ration and may not be copied or disclosed except in          *
;*      accordance with the terms of that agreement.                 *
;*                                                                   *
;********************************************************************/

MI_SW_BREAK_STRUC   STRUC
    allocated       DB  ?
    disarmed        DB  ?
    placed          DB  ?
    linear_address  DD  ?
    flat_address    DD  ?
    contents        DB  ?
MI_SW_BREAK_STRUC   ENDS

MI_HW_BREAK_STRUC   STRUC
    _allocated      DB  ?
    _linear_address DD  ?
    break_mode      DB  ?
    break_length    DB  ?
    task            DB  ?
MI_HW_BREAK_STRUC   ENDS

MI_LINK_STRUC   STRUC
    code_ptr    DP  ?
    next_link   DP  ?
MI_LINK_STRUC   ENDS

MI_STATIC_LINK_STRUC   STRUC
    _code_ptr   DP  ?
    link        DP  ?
    first_char  DB  ?
MI_STATIC_LINK_STRUC   ENDS

%*define (data)(
MIII_DATA   SEGMENT RW PUBLIC
)

%*define(data_ends)(
MIII_DATA   ENDS
)

%*define (code)(
MIII_CODE32 SEGMENT ER PUBLIC
)

%*define(code_ends)(
MIII_CODE32 ENDS
)

%*define (start) (
NAME config
%code
)

%set (RESET_DEFINED,0)
%*define (reset_proc(proc_name)) (
%SET (RESET_DEFINED,1)
%code_ends
EXTRN %proc_name:FAR
%code
PUBLIC MI_reset_ptr
MI_reset_ptr    DP  %proc_name
)

%*define (end) (

%IF (%interrupt_count GT 0) THEN (
%data
tss_storage DB  %interrupt_count * 68H DUP (?)
%data_ends

interrupt_list  DB  %interrupt_list 0

    PUBLIC MI_tss_from_rom
    EXTRN  MI_copy_tss:NEAR
MI_tss_from_rom PROC NEAR
            ; setup
            MOV     ECX, %interrupt_count
            MOV     EAX, OFFSET TSS_STORAGE
            
            ; for each non-zero entry in the interrupt_list,
            ; copy that TSS from ROM to RAM
loop_top:
            JCXZ    all_done
            PUSH    ECX
            PUSH    EAX
            MOV     BL, interrupt_list[ECX - 1]
            PUSH    EBX
            PUSH    DS
            PUSH    EAX
            CALL    MI_copy_tss
            POP     EAX
            POP     ECX
            DEC     ECX
            ADD     EAX,68H
            JMP     loop_top
all_done:
            RET
MI_tss_from_rom ENDP
)ELSE(
    PUBLIC MI_tss_from_rom
MI_tss_from_rom PROC NEAR
                RET
MI_tss_from_rom ENDP
)FI

; reset is optional, so clean up if not defined
%IF (NOT %RESET_DEFINED) THEN (
PUBLIC MI_reset_ptr
MI_reset_ptr    DP  0
) FI
; %interrupt_list
%code_ends
END
)

%*define (buffer_size(n))(
%data
PUBLIC MI_current_command
MI_current_command  DB  %n DUP (?)
PUBLIC MI_previous_command
MI_previous_command  DB  %n DUP (?)
%data_ends
PUBLIC MI_command_buffer_size
MI_command_buffer_size  DD  %n
)

%*define (version('string'))(
PUBLIC MI_version
MI_version  DB  '%string',0
)

%*define (newline('str'))(
PUBLIC MI_newline_value
MI_newline_value DB   %str, 0
)

%*define (sw_breaks(j))(
%data
PUBLIC MI_sw_break_strucs
MI_sw_break_strucs MI_SW_BREAK_STRUC %j DUP (<>)
%data_ends
PUBLIC MI_swbreak_count
MI_swbreak_count    DD  %j
)

%*define (hw_breaks(j))(
%data
PUBLIC MI_hw_break_strucs
MI_hw_break_strucs MI_HW_BREAK_STRUC %j DUP (<>)
%data_ends
PUBLIC MI_hwbreak_count
MI_hwbreak_count    DD  %j
)

%*define (parser_list_start) (
PUBLIC MI_static_parser_struc 
MI_static_parser_struc LABEL BYTE
)

%*define (parser(entry_point,'first_char'))local link_block(
%data
%link_block MI_LINK_STRUC <>
%data_ends
%code_ends
EXTRN %entry_point:FAR
%code
MI_STATIC_LINK_STRUC <%entry_point,%link_block,'%first_char'>
)

%*define (parser_list_end)(
MI_STATIC_LINK_STRUC <0,0,0>
)

; Macros to set up iM interrupt handlers
;
;   Essentially, we want to make an interrupt look like a procedure
;   call to M_wake_up
;
;   On entry to the interrupt       We want:
;   handler, the stack
;   looks like:     
;
;       |   old_eflags|                 |   hw_code   |
;       +-------------+                 +-------------+
;       |   old_cs    |                 |   reason    |
;       +-------------+                 +-------------+
;       |   old_eip   |                 |   old_cs    |
;       +-------------+                 +-------------+
;       -   hw_code   -                 |   old_eip   |
;       ---------------                 +-------------+
;
;   The hw_code is pushed by the following hardware faults ONLY:
;
;   8 (system error)
;  10 (invalid TSS)
;  11 (segment not present)
;  12 (stack fault)
;  13 (general protection)
;  14 (page fault)
;
;  faults 8, 10, and 12 should be handled by a hardware task
;

%define (interrupt_list)()
%set (interrupt_count, 0)

%*define (interrupt (vector, hw_code_present))local dummy(

MIII_CODE32    SEGMENT ER

PUBLIC  HW_VECTOR_%EVAL(%vector)

HW_VECTOR_%eval(%vector)    LABEL    FAR
        PUSH    %vector
        JMP     INT_HANDLER

MIII_CODE32    ENDS

%define (interrupt_list) (%interrupt_list %vector,)
%set (interrupt_count, %interrupt_count + 1)
)

%*define (yes)(1)
%*define (none)(0)

; equates are easiest to use
reason      EQU [ESP-4]
hw_code     EQU [ESP-8]

%*define (interrupt_start) (

MIII_CODE32    SEGMENT ER

INT_HANDLER PROC    NEAR
        CMP     DWORD PTR reason,9
        JE      FIXUP_STACK
        CMP     DWORD PTR reason,8
        JB      FIXUP_STACK
        CMP     DWORD PTR reason,14
        JBE     ASSEMBLE_ARGS

        ; we have no hw code - must deal with it properly
FIXUP_STACK:
        POP     EAX
        PUSH    0
        PUSH    EAX
        
        ; call M_wake_up
ASSEMBLE_ARGS:

        ; back to the debugger
        CALL    M_wake_up
        
INT_HANDLER ENDP

MIII_CODE32    ENDS
)
;